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J.W. Hines | lit.salon

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J.W. Hines

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Quick-turnaround ASIC design in VHDL: core-based behavioral synthesis1996
With Mohamed S. Ben Romdhane, N. Bouden-Romdhane, Vijay Madisetti

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Quick-turnaround ASIC design in VHDL: core-based behavioral synthesis1996
With Mohamed S. Ben Romdhane, N. Bouden-Romdhane, Vijay Madisetti
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